1. Field of the Invention
Embodiments of the invention are related to methods and configurations for preventing malfunctions, shortening delay times, reducing current consumption and/or reducing circuit areas for circuits, such as, for example, level shift circuits.
2. Description of the Related Art
In a half-bridge circuit in which switching elements are connected in series and driven by a high-potential power source, a level shift circuit is used for driving a high-potential-side switching element by a signal of a low-potential system. In a level shift circuit, a wire bonding system is sometimes used for connection between circuit blocks with a large difference in electrical potential, but the use of the wire bonding system adversely affects cost and product miniaturization capability because, for example, the number of operations is increased and a wiring space is necessary. Therefore, there is a demand for a level shift circuit using no wire bonding system. A level shift circuit using a parasitic resistor, such as described in Japanese Patent Publication No. 3941206 and Japanese Patent Publication No. 3214818, can be considered as a level shift circuit using no wire bonding system.
FIG. 1 shows the configuration of a half-bridge circuit 100 using the conventional level shift circuit which uses the techniques disclosed in Japanese Patent No. 3941206 and Japanese Patent Application Publication No. 2011-139423. The half-bridge circuit 100 shown in FIG. 1 is constituted by an output circuit 110, a high-potential-side drive circuit 120, and a low-potential-side drive circuit 130. The output circuit 110 is connected to the high-potential-side drive circuit 120 and the low-potential-side drive circuit 130. Synchronized signals are inputted from the outside to the high-potential-side drive circuit 120 and the low-potential-side drive circuit 130.
The output circuit 110 is configured of a switching element XD1, a switching element XD2, a power source E, and a load L1. In the output circuit 110, the switching element XD1 is connected in series with the switching element XD2 which is connected in parallel with the load L1, and the high-voltage power source E supplies power to the load L1 via the switching element XD1. The switching element XD1 is a high-potential-side switching element and can be, for example, an N-channel or P-channel MOS transistor or a P-type or N-type insulated gate bipolar transistor (IGBT). The switching element XD2 is a low-potential side switching element and can be, for example, an N-channel MOS transistor or an N-type IGBT. In the explanation below, the switching element XD1 and the switching element XD2 are assumed to be N-channel MOS transistors.
The high-potential-side drive circuit 120 is configured of a level shift circuit, a high-side driver 123, and a power source E1 (the output voltage thereof is also denoted by E1 hereinbelow). The level shift circuit is a component of the high-potential-side drive circuit 120, other than the high-side driver 123 and the power source E1, and configured of a latch malfunction protection circuit 121, a latch circuit 122, a first series circuit 124, a second series circuit 125, resistors R1 and R2 (the resistance values thereof are also denoted by R1 and R2, respectively), P-channel MOS transistors (referred to hereinbelow as PM) 1 and PM 2, a diode D1, a diode D2, an inverter INV, and a parasitic resistor Rpar3 present between the first series circuit 124 and the second series circuit 125. The latch malfunction protection circuit 121 receives input of a setdrn signal and a resdrn signal.
The first series circuit 124 is configured by connecting a parasitic resistor Rpar1 in a semiconductor substrate and a high-withstand-voltage N channel MOSFET (referred to hereinbelow as HVN) 1 in series and outputs a level shift output signal setdrn (referred to hereinbelow as setdrn signal) to the latch malfunction protection circuit 121 via a first connection point Vsetb (the potential thereof is also denoted by Vsetb). The first series circuit 124 is provided with a first level shift output terminal (that corresponds to the first connection point Vsetb) for outputting the setdrn signal to the latch malfunction protection circuit 121, and the first level shift output terminal is connected to the latch malfunction protection circuit 121.
The second series circuit 125 is configured by connecting a parasitic resistor Rpar2 in a semiconductor substrate and a HVN2 in series and outputs a level shift output signal resdrn (referred to hereinbelow as resdrn signal) to the latch malfunction protection circuit 121 via the HVN2 and a second connection point Vrstb (the potential thereof is also denoted by Vrstb). The second series circuit 125 is provided with a second level shift output terminal (corresponds to the second connection point Vrstb) for outputting the resdrn signal to the latch malfunction protection circuit 121, and the second level shift output terminal is connected to the latch malfunction protection circuit 121.
The PM1 is connected in parallel with the resistor Rpar1 constituting the first series circuit 124. The PM2 is connected in parallel with the resistor Rpar2 constituting the second series circuit 125. One end (connection point) of the resistor R1 is connected to a gate terminal of the PM2, and one end (connection point) of the resistor R2 is connected to a gate terminal of the PM1. A feedback circuit is constituted by the invertor INV, resistors R1 and R2, and PM1 and PM2. The parasitic resistances Rpar1 and Rpar2 and resistance values of the resistors R1 and R2 are assumed to satisfy the conditions: Rpar1=Rpar2 and R1=R2.
The latch malfunction protection circuit 121 receives input of the setdrn signal and resdrn signal. The latch malfunction protection circuit 121 serves to prevent the output from assuming a high impedance and adversely affecting the latch circuit 122 when an error signal called dV/dt noise which is caused by parasitic capacitances Cds1, Cds2 between sources and drains of HVN1, HVN2 (concerning the dV/dt noise, see, for example, Japanese Patent Application Publication No. 2011-139423) is generated, that is, when the potential Vsetb and the potential Vrstb are both at the L (Low) level. Except for the case in which the potential Vsetb and the potential Vrstb are both at the L (Low) level, the latch malfunction protection circuit 121 directly passes and outputs the setdrn signal and resdrn signal, or outputs signals obtained by processing based on the setdrn signal and resdrn signal (for example, the output signal is taken as 1 and is at the H level when the setdrn signal and resdrn signal set the latch circuit 122, the L level when the latch circuit is reset, and a high impedance when the latch circuit is not changed).
The latch circuit 122 is connected to the latch malfunction protection circuit 121 and the high-side driver 123. The latch circuit 122 receives the output from the latch malfunction protection circuit 121 and stores and outputs a value that is set or reset according to whether this input is L or H. Where the input is a high impedance, the latch circuit holds and outputs a value that has been stored immediately before the input became a high impedance.
The output terminal of the latch circuit 122 is connected through the resistor R2 to the second connection point Vrstb which is the connection point of the parasitic resistor Rpar2 and the HVN2 constituting the second series circuit 125. Further, the output of the latch circuit 122 is inverted by the inverter INV, whereby the inverted output of the latch circuit 122 is obtained. The output terminal of the inverter INV that outputs the inverted output is connected through the resistor R1 to the first connection point Vsetb which is the connection point of the parasitic resistor Rpar1 and the HVN1 constituting the first series circuit 124.
The high-side driver 123 is connected to the high-potential-side switching element XD1 and the latch circuit 122, outputs a signal HO in response to the output of the latch circuit 122, and ON/OFF controls the switching element XD1. The output terminal of the high-side driver 123 is connected to the gate terminal of the switching element XD1. The low-potential-side power supply terminals of the latch malfunction protection circuit 121, latch circuit 122, high-side driver 123, and power source E1 are connected to a connection point vs (the potential thereof is also represented by vs hereinbelow) of the switching elements XD1 and XD2. Further, the latch malfunction protection circuit 121, latch circuit 122, and high-side driver 123 receive the supply of power from the power source E1. The low-potential-side power supply terminal of the inverter INV is likewise connected to the connection point vs, and the inverter receives the supply of power from the power source E1 (this configuration is not shown in the figure).
One terminal of the first series circuit 124 and one terminal of the second series circuit 125 are connected to a power supply line vb (the potential thereof is also represented by vb hereinbelow) connected to the high-potential side terminal of the power source E1, and other terminals of the series circuits are connected to a ground potential (GND). A set signal, which is the input signal to the level shift circuit of the high-potential-side drive circuit 120, is inputted to the gate of the HVN1, and a reset signal, which is the input signal to the level shift circuit of the high-potential-side drive circuit 120, is inputted to the gate of the HVN2.
The diodes D1 and D2 are connected by the anodes thereof to the connection point vs of the switching elements XD1 and XD2, the cathode of the diode D1 is connected to the first connection point Vsetb, and the cathode of the diode D2 is connected to the second connection point Vrstb. The diodes D1 and D2 clamp the voltages Vsetb and Vrstb to prevent them from falling to or below the potential vs and protect the latch malfunction prevention circuit 121 from an overvoltage input.
The resistors R1 and R2 are connected to the potential vb or potential vs through a PMOS or an NMOS constituting a CMOS circuit or a CMOS circuit for logical inversion (INV) that is used in the latch circuit 122, but for the sake of simplicity, the PMOS and NMOS are not shown in the latch circuit 122. Such simplification is also used hereinbelow.
The low-potential-side drive circuit 130 is constituted by a low-side driver 131 that ON/OFF controls the low-potential-side switching element XD2, and a power source E2 (the potential thereof is also represented by E2 hereinbelow) that supplies power to the low-side driver 131.
The power from the power source E2 is supplied to the low-side driver 131, and a signal S inputted to the low-side driver 131 is amplified and inputted to the gate terminal of the switching element XD2. With such a configuration, when the signal S is at the H (High) level, the switching element XD2 is ON (conduction), and when the signal is at the L (Low) level, the switching element XD2 is OFF (disconnection). Thus, the signal S directly indicates ON/OFF of the switching element XD2.
As for the set signal and reset signal inputted to the high-potential-side derive circuit 120, the set signal indicates the ON period start (OFF period end) timing of the switching element XD1, and the reset signal indicates the OFF period start (ON period end) timing of the switching element XD2.
The switching elements XD1 and XD2 are complementary ON/OFF switched so that when one is ON, the other is OFF, except within the below-described dead time period. When the switching element XD2 is ON, the potential vs of the connection point vs becomes the ground potential, and when the switching element XD1 is ON, the potential vs of the connection point vs becomes the output voltage E of the power source E. Further, the load L1 receives the supply of power from the half-bridge circuit 100 and is connected between the connection point vs and the ground potential.
In this case, the resistance value of the parasitic resistor varies depending on temperature, power source voltage, and the like. FIG. 2 shows the dependence of the resistance value of the parasitic resistor on temperature. As shown in FIG. 2, when the temperature is −50° C., the resistance value of the parasitic resistor is 3 kΩ, and when the temperature is 150° C., the resistance value becomes 10 kΩ. FIG. 3 shows an example of the dependence of the resistance value of the parasitic resistor on power source voltage. As shown in FIG. 3, when the vb-GND voltage is 0 V, the resistance value of the parasitic resistor is 3 kΩ, and when the vb-GND voltage is 800 V, the resistance value becomes 30 kΩ. Thus, the resistance value of the parasitic resistor, which is the resistor in the semiconductor substrate, shows dependence on temperature and dependence on power source voltage. Therefore, the rise time of the setdrn signal and resdrn signal changes depending on temperature or power source voltage conditions and can adversely affect the operation of the level shift circuit, as described hereinbelow.
Further, the resistance value of the parasitic resistor Rpar3 present between the first series circuit 124 and the second series circuit 125 changes depending on the distance between the HVN1 and the HVN2. FIG. 4 shows the dependence of the resistance value of the parasitic resistor Rpar3 on the distance between the HVN1 and the HVN2. As shown in FIG. 4, when the distance between the HVN1 and the HVN2 is 1000 the resistance value of the parasitic resistor Rpar3 is 500 kΩ.
In the level shift circuit shown in FIG. 1, for example, the resistance values of the parasitic resistors Rpar1 and Rpar2 are adjusted to about 10 kΩ, and the resistance value of the parasitic resistor Rpar3 is adjusted to about 500 kΩ. By increasing the resistance value of the parasitic resistor Rpar3, it is possible to reduce the adverse effect produced during operation of each level shift circuit.
In the half-bridge circuit 100 shown in FIG. 1, by connecting the output of the latch circuit 122 and the output of the inverter INV to one end of the resistors R1 and R2, it is possible to make the potential at one end of the resistors R1 and R2 equal to the potential vb or potential vs according to the output state of the latch circuit 122. When the output HO is at the L level (when the latch circuit 122 is in the reset state), the potential at one end of the resistor R1 is the potential vb, the parasitic resistor Rpar1 and the resistor R1 are in the parallel connection state, the potential at one end of the resistor R2 is the potential vs, and the parasitic resistor Rpar2 and the resistor R2 are in the series connection state. Therefore, the gate potential of the PM1 becomes lower than the potential vb, and the PM1 is not in the completely disconnected state, whereby the impedance between the first connection point Vsetb and the power source line vb is decreased. Meanwhile, when the gate potential of the PM2 is the potential vb and the PM2 is in the disconnected state, the impedance between the second connection point Vrstb and the power source line vb becomes higher than that in the case of the first connection point Vsetb. Further, since the potential at one end of the resistor R2 becomes the potential vs, the second connection point Vrstb is pulled down to the potential vs side. The output impedance against the potential vb of the connection point is lower for the first connection point Vsetb than for the second connection point Vrstb.
When the output HO is at the H level (when the latch circuit 122 is in the set state), the parasitic resistor Rpar1 and the resistor R1 are in the series connection state and the parasitic resistor Rpar2 and the resistor R2 are in the parallel connection state. The gate potential of the PM2 becomes lower than the potential vb, and the PM2 is not in the completely disconnected state, whereby the impedance between the second connection point Vrstb and the power source line vb is decreased. Meanwhile, when the gate potential of the PM1 is the potential vb and the PM1 is in the disconnected state, the impedance between the first connection point Vsetb and the power source line vb becomes higher than that in the case of the second connection point Vrstb. Further, since the potential at one end of the resistor R1 becomes the potential vs, the first connection point Vsetb is pulled down to the potential vs side. The output impedance against the potential vb of the connection point is higher for the first connection point Vsetb than for the second connection point Vrstb.
Therefore, the latch circuit 122 is configured to be set or reset anew so that even when the dV/dt noise occurs and both the potential of the first connection point Vsetb and the potential of the second connection point Vrstb decrease, the two potentials return to the H level at different speeds and the potential with the lower return speed eventually holds the state preceding the occurrence of the dV/dt noise, thereby making it possible to avoid the effect of the dV/dt noise.
FIG. 5 shows an operation time chart of the level shift circuit shown in FIG. 1. Where the input pulse of the set signal is switched to the H level at a point of time t1, the setdrn signal decreases to the potential vs and the latch output starts rising to the H level. As long as the input pulse of the set signal is at the H level, the setdrn signal is continuously at the level of potential vs. Where the output of the latch circuit 122 is switched from the L level to the H level at a point of time t2, the parallel/series connection states of the resistors R1 and R2 are switched. Where the input pulse of the set signal is switched from the H level to the L level at a point of time t3, the setdrn signal rises. Where the input pulse of the reset signal is switched to the H level at a point of time t4, the resdrn signal decreases to the potential vs and the latch output starts decreasing to the L level. As long as the input pulse of the reset signal is at the H level, the resdrn signal is continuously at the level of potential vs.
Where the output of the latch circuit 122 is switched from the H level to the L level at a point of time t5, the parallel/series connection states of the resistors R1 and R2 are switched. Where the input pulse of the reset signal is switched from the H level to the L level at a point of time t6, the resdrn signal rises.
Where the inversion (setting) timing of the output of the latch circuit 122 is earlier than the input pulse width of the set signal, the impedance of the output of the first series circuit 124 at the time the setdrn signal starts rising is in the high state, the time constant of the time constant circuit constituted by the first series circuit and the parasitic capacitor Cds1 increases and the connection to the level of potential vs through the resistor R1 is realized. Therefore, the rise of the setdrn signal is delayed.
Further, since the parasitic resistors Rpar1 and Rpar2 are used as level shift resistors, this rising time changes, as described hereinabove, under the effect of temperature and power source voltage. As shown in FIG. 2 and FIG. 3, where the temperature or voltage increases, the resistance values of the parasitic resistors Rpar1 and Rpar2 increase. Where the resistance values of the parasitic resistors Rpar1 and Rpar2 thus increase, the delay of the rise of the setdrn signal and resdrn signal increases, but where the pulses of the set signal and reset signal are generated separately, even if the rise of the setdrn signal and resdrn signal is somewhat delayed, this delay causes no problem. However, the setdrn signal and resdrn signal are both at the L level in the case where the resistance values of the parasitic resistors Rpar1 and Rpar2 are large, the set signal—reset signal pulse spacing is narrow, the pulses of the set signal and reset signal are generated continuously, and the subsequent pulse falls while the preceding pulse is still rising. Where the setdrn signal and resdrn signal are both at the L level, the state identical to that in which the dV/dt noise occurs is realized, the resultant shortcoming being that the setdrn signal or resdrn signal which intrinsically should pass therethrough by the latch malfunction protection circuit 121 is blocked. Therefore, the subsequent pulse becomes effective after the preceding pulse has risen, the delay time increases, as shown in FIG. 5, and the responsiveness is degraded. Where the resistance value of the level shift resistor is decreased in order to avoid such a shortcoming associated with the occurrence of a period in which both the setdrn signal and the resdrn signal are at the L level, even if the signals are normal, when the HVN is ON and the dV/dt noise occurs, the electric current flowing in the level shift resistor increases and current consumption rises.
FIG. 6 shows circuit simulation results obtained for the half-bridge circuit 100 shown in FIG. 1 in the case where the set signal—reset signal pulse spacing is 0.5 μs. FIG. 7 shows circuit simulation results obtained for the half-bridge circuit 100 shown in FIG. 1 in the case where the set signal—reset signal pulse spacing is 0.2 μs. As shown in FIG. 6, where the set signal—reset signal pulse spacing is 0.5 μs, the output waveform of the latch output when the resistance value of the parasitic resistor is 5 kΩ (shown by a broken line) is the same as that when the resistance value of the parasitic resistor is 35 kΩ (shown by a solid line)
However, as shown in FIG. 7, where the output waveform when the resistance value of the parasitic resistor is 5 kΩ is compared with the output waveform when the resistance value of the parasitic resistor is 35 kΩ in the case in which the set signal—reset signal pulse spacing is 0.2 μs, a delay caused by a block in the latch malfunction prevention circuit 121 occurs in the output waveform of the latch output when the resistance value of the parasitic resistor is 35 kΩ. Therefore, a level shift circuit is needed in which the delay time is not affected, regardless of the set signal—reset signal pulse spacing and the resistance values of parasitic resistors. Thus, as described above, there is a need in the art for an improved level shift circuit.